The present invention relates to a semiconductor memory device, and more particularly, to a technology for controlling a read cycle of a semiconductor memory device.
A semiconductor memory device continuously outputs the number of bits of data depending on a Burst length BL. For a burst length BL of 4, 4 bits of data are continuously outputted, and for a burst length BL of 8, 8 bits of data are continuously outputted. Therefore, a duration of a read cycle of the semiconductor memory device varies depending on a set value of the burst length BL.
FIG. 1 is a block diagram of a circuit for controlling a conventional read cycle.
As shown in FIG. 1, the circuit for controlling the conventional read cycle includes an SR latch 110, and a counter block 120.
The SR latch 110 activates a read cycle signal ROUTEN in response to a read signal RD, and inactivates a read cycle signal ROUTEN in response to a reset signal RST.
The counter block 120 activates the reset signal RST after 2 clock cycles or 4 clock cycles from a timing point at which read cycle signal ROUTEN is activated. The timing point at which the counter block activates the reset signal is determined by burst setting information. When the burst length BL is set to 8, the counter block activates a reset signal RST after 4 clock cycles from the timing point at which the read cycle signal ROUTEN is activated. When the burst length BL is set to 4, the counter block activates a reset signal RST after 2 clock cycles from the timing point at which the read cycle signal ROUTEN is activated.
The read signal RD is activated when a read commend is applied from an outside of a chip, and the read cycle signal ROUTEN is used to define a period at which bits of data are outputted from the memory device. Therefore, the read cycle signal ROUTEN has a period varied depending on the burst length BL.
FIGS. 2A and 2B are timing diagrams illustrating an operation of FIG. 1.
FIG. 2A illustrates an operation of the circuit for controlling the read cycle when the burst length BL is set to 4 (in a BC4 mode for DDR3 where a BL4 is impossible in principle). FIG. 2B illustrates an operation of the circuit for controlling the read cycle when the burst length BL is set to 8.
Referring to FIG. 2A, the SR latch 110 activates the read cycle signal ROUTEN simultaneously while the read signal RD is active.
The counter block 120 activates the reset signal RST after 2 clock cycles from the timing point at which the read cycle signal ROUTEN is activated. Then, the SR latch 110 inactivates the read cycle signal ROUTEN in response thereto. In this case, the read cycle signal ROUTEN is active for 2 clock cycles, which corresponds to time required for stream output of 4 bits of data.
Referring to FIG. 2B, the SR latch 110 activates the read cycle signal ROUTEN simultaneously with the activation of the read signal RD. The counter block 120 activates the reset signal RST after 4 clock cycles from the timing point at which the read cycle signal ROUTEN is activated. Then, the SR latch 100 inactivates the read cycle signal ROUTEN in response thereto. In this case, the read cycle signal ROUTEN is active for 4 clock cycles, which corresponds to time required for stream output of 8 bits of data.
FIG. 3 is a timing diagram illustrating a problem with respect to the circuit for controlling the conventional read cycle shown in FIG. 1 when a read command is continuously applied.
Due to a short margin for distinguishing signals in the semiconductor memory device, the reset signal RST is not activated at an accurate timing, and is activated after a slight delay. FIG. 3 illustrates such a problem.
As shown in FIG. 3, when a reset signal RST 304 corresponding to a first read signal RD 301 is activated at a timing later than that of a second read signal RD 302, a read cycle signal ROUTEN corresponding to the second read signal RD 302 is inactivated simultaneously while the reset signal RST 304 is active. Therefore, in this case, a read cycle corresponding to the second read signal RD 302 is skipped, and a read operation fails to be performed in the memory device.